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at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 1 qualification package at89c51ed2 flash 8 - bit c51 microcontroller 64 kbytes flash, 2 kbytes eeprom at89c51rd2 / at89c51ed2 july 2003
at89c51rd2 / at89c51ed2 qualpack 2 rev. 0 ? 2003 jul y 1 table of contents 1 table of contents ................................ ................................ ................................ ................................ ............. 2 2 general information ................................ ................................ ................................ ................................ ...... 3 3 technology informat ion ................................ ................................ ................................ ............................ 4 3.1 w afer p rocess t echnolo gy ................................ ................................ ................................ .............................. 4 3.2 p roduct d esign ................................ ................................ ................................ ................................ ................... 5 3.3 d evice cross section ................................ ................................ ................................ ................................ .......... 6 4 qualification ................................ ................................ ................................ ................................ ...................... 7 4.1 q ualification m ethodology ................................ ................................ ................................ ............................ 7 4.2 q ualification t est m ethods ................................ ................................ ................................ ............................. 8 4.3 w afer l evel r eliability ................................ ................................ ................................ ................................ ... 9 4.3.1 electromigration ................................ ................................ ................................ ................................ ............... 9 4.3.2 hot carriers injection ................................ ................................ ................................ ................................ ..... 11 4.3.3 time dependent dielectric breakdown ................................ ................................ ................................ ............ 12 4.3.4 flash characteristics ................................ ................................ ................................ ................................ .... 14 4.4 d evice r eliability ................................ ................................ ................................ ................................ ............ 18 4.4.1 operating life testing ................................ ................................ ................................ ................................ ..... 18 4.4.2 esd / latch - up ................................ ................................ ................................ ................................ ................ 18 4.4.3 flash and eeprom data ret ention and endurance cycling ................................ ................................ ........ 18 4.4.4 at89c51ed2 operating reliability calculation ................................ ................................ .............................. 20 4.5 at89c51ed2 p ackaging reliability ................................ ................................ ................................ ............... 21 4.6 at89c51ed2 q ualification status ................................ ................................ ................................ ................ 21 5 environmental inform ation ................................ ................................ ................................ .................... 22 6 othe r data ................................ ................................ ................................ ................................ .......................... 23 6.1 iso / ts16949 : 2002 c ertificate ................................ ................................ ................................ ..................... 23 6.2 d ata b ook r eference ................................ ................................ ................................ ................................ ...... 24 6.3 r evision h istory ................................ ................................ ................................ ................................ .............. 24
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 3 2 general information product name: at89c51rd2 function: 8 - bit microcontroller with 64 kbytes flash spi interface product name: at89c51e2 function: 8 - bit microcontroller with 6 4 kbytes flash, 2 kbytes eeprom spi interface wafer process: logic cmos 0.35 um with embedded flash available package types plcc 44, vqfp 44, plcc 68, vqfp 68 ,pdil 40 other forms: die, wafer locations: process development, atmel colorad o springs, usa product development atmel nantes, france wafer plant atmel colorado springs, usa qc responsibility atmel nantes, france probe test atmel colorado springs, usa assembly depending on package final test atmel tsti manila, philippines l ot release atmel nantes, france shipment control global logistic center, philippines quality assurance atmel nantes, france reliability testing atmel nantes, france failure analysis atmel nantes, france quality management atmel nantes, france signed: pascal lecuyer
at89c51rd2 / at89c51ed2 qualpack 4 rev. 0 ? 2003 jul y 3 technology information 3.1 wafer process technology process type (name): logic 0.35um with embedded flash (at56800) base material: epitaxied silicon wafer thickness (final) 475 um wafer diameter 1 50 mm number of masks 27 gate oxide (logic transistors) material silicon dioxide thickness 68a gate oxide (eprom cell) material silicon dioxide thickness 390a polysilicon number of layers 2 thickness poly 1 1400a amorphous thickness po ly 2 3200a metal number of layers 3 material: aluminum copper layer 1 thickness 5000a layer 2 thickness 5000a layer 3 thickness 8000a passivation material oxide hdp/ oxy - nitride thickness 21000a
at89c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 5 3.2 product design die size 17,9 mm 2 pad size opening / pitch 66 um * 66 um / 111 um logic effective channel length 0.35 m gate poly width (min.) 0.35 m gate poly spacing (min.) 0.42 m metal 1 width 0.42 m metal 1 spacing 0.49 m metal 2 width 0.56 m metal 2 spacing 0.49 m metal 3 width 0.56 m metal 3 spacing 0.49 m contact size 0.35 m contact spacing 0.42 m via 1 size 0.42 m via 2 size 0.42 m
at89c51rd2 / at89c51ed2 qualpack 6 rev. 0 ? 2003 jul y 3.3 device cross section at56kxx cross section
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 7 4 qualifi cation 4.1 qualification methodology all product qualifications are split into three distinct steps as shown below. before a product is released for use, successful qualification testing are required at wafer, device and package level. - wafer level rel iability consists in testing individually basic process modules regarding their well known potential limitations (electro - migration, hot carriers injection, oxide breakdown, nvm data retention). each test is performed using wafer process specific structure s. - device reliability is covering either dice design and processing aspects. the tests are performed on device under qualification, but generic data may also be considered for reliability calculation. - for each package type proposed in the datasheet, it i s verified that qualification data are available. if not qualification tests are carried out for the new package types. in addition, one package type is selected to verify packaging reliability of the device under qualification. product qualification wafer level reliability device reliability packaging reliability (design / process)
at89c51rd2 / at89c51ed2 qualpack 8 rev. 0 ? 2003 jul y 4.2 qualification test met hods general requirements for plastic packaged cmos ics: standard test description acceptance mil - std 883 method 1005 electrical life test (early failure rate) 48 hours 140c 0/300 - 48h mil - std 883 method 1005 electrical life test (latent failure rate) 1000 hours 140c dynamic or static 0/100 - 500h mil - std 883 method 3015.7 electrostatic discharge hbm +/ - 2000v 1.5kohm/100pf/3 pulses 0/3 per level jedec 78 latch up 50mw power injection, 50% overvoltage @125c 0/5 per stress aec q100 method 005 nvm endurance program erase cycles 25c 0/50 - 10kc aec q100 method 005 nvm data retention high temperature storage 165c 0/50 - 500h mil - std 883 method 1010 temperature cycling 1000 cycles ? 65c/150c air/air 0/50 - 500c atmel paqa0184 hast after preconditioning 144 hours 130c/85%rh 0/50 ? 96h eia jesd22 - a101 85/85 humidity test 1000 hours 85c/85%rh 0/50 - 500h eia jesd22 - a110 hast 336 hours 130c/85%rh 0/50 - 168h eia jedec 20 - std preconditioning soldering stress 220c/235c/3 times 0/11 per class mil - std 883 method 2003 solderability 0/3 mil - std 883 method 2015 marking permanency 0/5
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 9 4.3 wafer level reliability 4.3.1 electromigrati on purpose: to evaluate the at56800, at35500, and at37000 processes for metal 1, metal 3 & via electromigration reliability. these 3 processes have the same steps for interconnect levels. test parameters: metal 1 & metal 3: sample size = 15 temp = 25 0c with joule heating . j = 3.5e06 a/cm2. via: sample size = 15 temp = 200c with joule heating. j = 2.5e06 a/cm2. black?s equation parameters: failure criteria - 10% increase in resistance. data taken every 1% change. n = 2 ea = 0.6ev lifetime predicti ons: metal 1 : split 1 - tf .1% exp = ~ 28 hrs tf .01% op = ~ 28 hrs x 39706 accel = 127 years . (sigma = 2.7118 hours, accel temp = 130, accel current = 306) metal 3 : split 3 - tf .1% exp = ~ 140 hrs tf .01% op = ~ 140 hrs x 39706 accel = 634 years . (sigma = 1.8782 hours, accel temp = 130, accel current = 306) via : split 4 - tf .1% exp = ~ 22 hrs tf .1% op = ~ 22 hrs x 7144 accel = 18 years . (sigma = 2.59 hours, accel temp = 31.75, accel current = 225) (9/15 fails) conclusion: all splits pass th e minimum 10 years lifetime.
at89c51rd2 / at89c51ed2 qualpack 10 rev. 0 ? 2003 jul y test results : at56800 metal 1 results at56800 metal 3 results at56800 via results electromigration summary table: level sample size fails @ 10% tf.1% lifetime (yrs) m1 15 9 140 m3 15 7 1088 via 15 9 19
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 11 4.3.2 hot carriers injection test conditions the test is performed by forcing a high drain bias on the test device (vds>vddmax) to accelerate the carriers to the maximum. at the same time the gate bias (vgs) is chosen in order to maximize the injection of carriers into the gate oxide and also the substrate. wlr_b n - channel w/l 0.35um/25um the stress is performed on a number of transistors, each at a different stress condition vds,stress and vgs,stress. for each transistor, the time to reach the failure criteria (didsat/idsat=10%) is obtained. nmos is more sensitive to hot carriers compared to pmos. consequently nmos is the only structure tested. measurement at568t7 lot 1j0433 has been measured using the wlr_b hot electron structure with standard drain . nmos w/l = 25/0.35 um. results hci 56.8k 1j0433 at568t7 fab 5 n-channel w/l 0.35/25.0um 10% change in idsat y = 5e+16x 30,692 r 2 = 0,9719 0,0001 0,001 0,01 0,1 1 0,2 0,22 0,24 0,26 0,28 0,3 1/vdd tau lifetime in years conclusion the extrapolated life time in the worst case conditions (@vds=vdd max & vgs set to maximize substrate current) is much greater than 0.2 years in dc mode (qualification requireme nt) which is equivalent to more than 10 years in ac mode.
at89c51rd2 / at89c51ed2 qualpack 12 rev. 0 ? 2003 jul y 4.3.3 time dependent dielectric breakdown purpose: to evaluate the at56800 thin gate oxide tddb performance as follows: a) to determine the activation energy of gate oxide failures on sti active edge capacitors b) to determine the field acceleration factor for intrinsic gate oxide failures c) to determine the sigma the lognormal standard deviation of the time to breakdown distribution of the intrinsic gate oxide test parameters: lot 9g3470 (wafers 4, 5, 18) min thickness: 72.9a max thickness: 74.7a capacitor size: 6.267 um 2 the stress conditions used are shown below: temperature/field 9.5mv/cm 10.0mv/cm 10.5mv/cm 225c n=5 n=5 n=5 200c n=5 n=5 n=5 175c n=5 n=5 n=6 accumulated total stress time: 1 32 hours / 46 capacitors calculation parameters: failure criteria: 0.01% failures temp/voltage use: 105c / 3.3v oxide thickness: 63a (target ? 10%) lifetime prediction: the equation used to describe the breakdown of gate oxides is: tbd(i) = exp(sigma *z(i) + gamma*eox +ea/kt + t0) where tbd(i) is the time to breakdown of the i th capacitor, sigma is the lognormal standard deviation of the breakdown distribution, z(i) is the z - score of the i th capacitor (essentially the difference between its breakdo wn time and the mean measured in standard deviations), gamma is the field acceleration constant, eox is the oxide field, ea is the activation energy of this failure mechanism, k is boltzmann?s constant, t is the kelvin temperature, and t0 is a fitting c onstant.
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 13 the best fit coefficients in the regression analysis are: t0= 14.25034317 ln - sec ea= 1.060043152 ev gamma= - 3.2454227 ln - sec - cm/mv sigma= 0.414655753 ln - sec with an adjusted r - squared of 97.99%. the intrinsic lifetime at use conditions calcula ted from this regression is 56174 years. conclusion: using the coefficients determined above, the time to reach any cumulative percent failure level can be estimated given the stress conditions. using 105c and 3.3 volts on 63 angstrom n - channel gate2 oxi de, we may expect 0.01% of capacitors having 6,267 square microns area with 6,174 microns of active edge to fail in about 613 years, exceeding the technology requirement of ten years. test results : at56.8k active edge tddb 225c -2,00000e+00 -1,00000e+00 0,00000e+00 1,00000e+00 2,00000e+00 1,00 e+00 1,00 e+01 1,00 e+02 1,00 e+03 1,00 e+04 1,00 e+05 tbd (sec) at56.8k active edge tddb 200c -2,00000e+00 -1,00000e+00 0,00000e+00 1,00000e+00 2,00000e+00 1,00 e+00 1,00 e+01 1,00 e+02 1,00 e+03 1,00 e+04 1,00 e+05 tbd (sec) at56.8k active edge tddb 175c -2,00000e+00 -1,00000e+00 0,00000e+00 1,00000e+00 2,00000e+00 1,00 e+00 1,00 e+01 1,00 e+02 1,00 e+03 1,00 e+04 1,00 e+05 tbd (sec)
at89c51rd2 / at89c51ed2 qualpack 14 rev. 0 ? 2003 jul y 4.3.4 flash characteristics 4.3.4.1 cell endurance purpose: to evaluate the ability of memory cell to withstand high number of program/erase cycles without change of electrical characteristics. test parameters: mea surements have been done on lot 0r5414. test done on 2 cells in a byte : - cell near byte select transistor, called bit0 (1 st column) - cell near vss contact, called bit 7 (8 th column). cycling is done for various programming voltages : - write : 13.5v on b l / 15.6v on select - clear : 13.5v on sense / 15.6v on select @5ms 14.5v on bl / 16.6v on select @5ms 14.5v on sense / 16.6v on select 15.5v on bl / 17.6v on select 15.5v on sense / 17.6v on select 16.5v on bl / 17.6v on select 16.5v on sense / 17.6v o n select mp044 0r5414 #01 vsel=vbl+2.1 bit 0 (near byte sel) -2.5 -2 -1.5 -1 -0.5 0 1 10 100 1000 10000 100000 # cycles vt_wrt (v) 13.5v 14.5v 15.5v 16.5v mp044 0r5414 #01 vsel=vbl+2.1 bit 7 (near vss) -2.5 -2 -1.5 -1 -0.5 0 1 10 100 1000 10000 100000 # cycles vt_wrt (v) 13.5v 14.5v 15.5v 16.5v mp044 0r5414 #01 vsel=vsen+2.1 bit 0 (near byte sel) 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 1 10 100 1000 10000 100000 # cycles vt_clr (v) 13.5v 14.5v 15.5v 16.5v mp044 0r5414 #01 vsel=vsen+2.1 bit 7 (near vss) 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 1 10 100 1000 10000 100000 # cycles vt_clr (v) 13.5v 14.5v 15.5v 16.5v
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 15 conclusions: - vt_wrt shift of 200 mv after 10k cycles - i_read decrease of 2.5 ua after 10kcycles ( - 7 to 9 %) - no big difference between bit0 and bit 7 in terms of vt or current variations using the coefficients 4.3.4.2 cell retention purpose: to extrapolate cell life duration at 125c from bake measurements at high temperature. test parameters: lot: 9t0930 temperature: 250c and 200c dura tion: 92 hours lifetime prediction: the equation used to describe memory cell retention is: dvt (v) = a * (t[h])^m * exp ( - 1.05ev/kt[k]) results : 56.8k cell - 9t0930 (#24/25) y = 0,2138ln(x) - 2,3118 y = 0,2211ln(x) - 4,8026 -5 -4 -3 -2 -1 0 1 10 100 bake time (h) ln [dvt (v)] 200c 250c 150,0 170,0 190,0 210,0 230,0 250,0 270,0 290,0 1 10 100 1000 10000 100000 time (h) t (c) test measurements extrapolated life time conclusions : extrapolation to 125c - 10years = vt loss is less than 0.8 mv
at89c51rd2 / at89c51ed2 qualpack 16 rev. 0 ? 2003 jul y 4.3.4.3 cell read disturb purpose: to measure read disturb influence on 56k8 memory cell. test parameters: lot: 0t0348 programming: 14v on wl and sensegate @5ms temperature: 25 c and 140c the cell is stressed with bl voltage much higher than standard read conditions (around 6v) to accelerate disturb phenomenon : electrons from the floating gate can move through the tunnel oxide. this charge loss is measured after stress by a vt measurement. test results: conclusion: extrapolation to 10 years lifetime give a maximum bl voltage of around 4v in read operation, which is much higher than nominal bl read voltage (~1v). so there is no sensitivity to read disturb either at ro om temperature or high temperature. 0t0348 #01 56.8k (568a6) bl read disturb @140c 0 0.5 1 1.5 2 2.5 0.1 1 10 100 1000 10000 time (s) delta vt (v) vbl=6v vbl=6.5v vbl=7v vbl=7.5v vbl=8v 0t0348 #01 56.8k (568a6) bl read disturb @25c 0 0.5 1 1.5 2 2.5 0.1 1 10 100 1000 10000 time (s) delta vt (v) vbl=6v vbl=6.5v vbl=7v vbl=7.5v vbl=8v
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 17 4.3.4.4 wafer probe data retention measurement data retention has been verified after bake for 168 hours at 250c on 3 wafers of a standard production lot. the results are summarized in the table below: lot wafer % retention loss failure rate extrapolation at 55c time to failure 1g4448 6 0% 3.91fit >> 10 years 1g4448 8 0% 4.19fit >> 10 years 1g4448 12 0% 3..96fit >> 10 years total 0% 1.34fit >> 10 years conclusion : data retention measurements at wafer probe stand o ut high data retention capability of at56800 products, exceeding the technology requirement of ten years .
at89c51rd2 / at89c51ed2 qualpack 18 rev. 0 ? 2003 jul y 4.4 device reliability 4.4.1 operating life testing at89c51ed2 test results are summarized in the table below. lot device type test descr iption step result comment a01948k at89c51ed2 plcc 44 efr dynamic life test 12h 48h 0/300 0/300 lfr dynamic life test 500h 1000h 0/100 0/100 4.4.2 esd / latch - up at89c51ed2 test results are summarized in the table below. lot device type test description step result comment a01948 at89c51ed2 plcc 44 esd - hbm model 2000v 3000v 4000v 5000v 0/3 1/3 1/3 1/3 class 2 of mil std 883 latch - up over - voltage power injection 5.5v 50mw 0/5 0/5 test done at 125c classified latch - up fr ee 4.4.3 flash and eeprom data retention and endurance cycling at89c51ed2 test results are summarized in the table below. lot device type test description step result comment a01948k at89c51ed2 plcc 44 data retention 500h 1000h 0/50 0/50 program / erase endurance cycling 100kc 0/30 32k user memory program / erase endurance cycling 100kc 0/30 2k data memory
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 19 at56800 program / erase endurance : temperature acceleration factor calculation: 0 10000 30000 50000 70000 90000 110000 number of cycles 0 5 10 15 legend normal (94541;13074) weibull (100021;8,97;0) fail count a01110 - 125d endurance 16k flash program erase endurance: ty pical 125d distribution endurance temperature acceleration t89c51cc02 - a01013l 1076331 94415 1,0e+03 1,0e+04 1,0e+05 1,0e+06 1,0e+07 25c 125c nc(50%) temperature effect on 16k flash program / erase a t(125d/25d) = 11.8 - ea = 0.25ev at56800 flash / eeprom reliability calculation : global calculation at56800 microcontrollers data - retention test 165c 250c 0/1101000 0/251496 for current sample size expressed in device*hours, ea = 0.7ev, cl = 60%, t = 55: ? dr = 0.29 fit endurance cycling 55c 1/109850k failure : 1 bit charge loss for sample size expressed in equivalent cycles at 55c, and assuming one cycle per day, ea = 0.25ev, cl = 60%: ? ec = 0.76 fit
at89c51rd2 / at89c51ed2 qualpack 20 rev. 0 ? 2003 jul y 4.4.4 at89c51ed2 operating reliability calculation in the next table, it is proposed a at89c51ed2 reliability prediction calculated at 55c for 60% confidence level from generic test data colle cted over the 12 last months process monitor. lots device type test description step result comment a00648 p01709 a00988b t89c51cc01 vqfp 44 efr dynamic life test 48h 0/3787 a01459a a01460e a01615b lfr dynamic life test 1000h 0/266 a01110c a011 10d t89c51cc02 soic28 efr dynamic life test 48h 1/1260 1 ipd drift caused by scratch on metal 1 a01185f a01366e lfr dynamic life test 1000h 0/280 a01679a a01679b t89c51rc2 plcc 44 efr dynamic life test 48h 0/1856 lfr dynamic life test 1000h 0/1 00 a00808a a00943e t89c51rb2 plcc 44 efr dynamic life test 48h 0/300 lfr dynamic life test 1000h 0/100 a01487q a02179 t85c5121 t89c5121 efr dynamic life test 48h 0/684 ssop24 lfr dynamic life test 1000h 0/100 a01435h a01435k at89c5114 soi c20 efr dynamic life test 48h 0/1887 a02293c lfr dynamic life test 1000h 0/200 a00960c a01808a at89c51snd1 at83c51snd1 efr dynamic life test 48h 1/550 consumption hot spot in dclk input buffer a01914j vqfp 80 lfr dynamic life test 1000h 0/170 a01584a at89c5131 vqfp64 efr dynamic life test 48h 0/350 lfr dynamic life test 1000h 0/100 global efr dynamic life test 48h 2/10674 187 ppm lfr dynamic life test - 0/1316 4.4 fit
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 21 4.5 at89c51ed2 packaging reliability in this section are presented the packaging qualification measurements carried out in plcc 44. lots device type test description step result comment a01948k at89c51ed2 plcc 44 humidity 85/85 post preconditioning level 1 500h 0/50 0/50 thermal cycles post preconditioning l1 500c 1000c 0/50 0/50 autoclave post thermal shocks and precond. l1 96h 0/50 a01679c at89c51rc2 plcc44 preconditioning level 1 sam visual elect. 0/11 0/50 0/50 thermal cycles post preconditioning l1 500c 1000 c 0/50 0/50 humidity 85/85 post preconditioning level 1 500h 0/50 0/50 autoclave post thermal shocks and precond. l1 96h 0/50 high temperature storage 500h 1000h 0/50 0/50 marking permanency visual 0/5 4.6 at89c51ed2 qual ification status atmel digital 0.35 um wafer process is qualified since 1999, october. derived from this technology, at89c51rd2 / at89c51ed2 have passed successfully reliability testing. full qualification has been pronounced in june 2003. all package p ass level 1 of moisture sensitivity ranking as per jesd 20b. therefore, dry packing is not mandatory.
at89c51rd2 / at89c51ed2 qualpack 22 rev. 0 ? 2003 jul y 5 environmental information atmel nantes environmental policy aims are : - reducing the use of harmful chemicals in its processes - reducing the content of harmful materials in its products - using re - usable materials wherever possible - reducing the energy content of its products as part of that plan, ozone depleting chemicals are being replaced either by atmel nantes or its sub - contractors. atmel nantes site is iso14001 certified since may 2000 .
at89 c51rd2 / at89c51ed2 qualpack rev. 0 ? 2003 july 23 6 other data 6.1 iso / ts16949 : 2002 certificate
at89c51rd2 / at89c51ed2 qualpack 24 rev. 0 ? 2003 jul y 6.2 data book reference the data sheet is available upon request to sales representative or upon direct access on atmel web site: http://www.atmel.com/ addres s references all inquiries relating to this document should be addressed to the following: atmel nantes bp70602 44306 nantes cedex 3 france telephone (33) 2 40 18 18 18 telefax (33) 2 40 18 19 00 or direct contact pascal lecuyer telephone (33) 2 40 18 17 73 telefax (33) 2 40 18 19 46 6.3 revision history issue modification notice application date 0 initial product evaluation 2003 july remarks: the information given in this document is believed to be accurate an d reliable. however, no responsibility is assumed by atmel for its use. no specific guarantee or warranty is implied or given by this data unless agreed in writing elsewhere. atmel reserves the right to update or modify this information without notificatio n, at any time, in the interest of providing the latest information. parts of this publication may be reproduced without special permission on the condition that our author and source are quoted and that two copies of such extracts are placed at our dispos al after publication. before use of such reproduced material the user should check that the information is current. written permission must be obtained from the publisher for complete reprints or translations

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